1. Field of the Invention
The present invention relates to twin MONOS memory and more particularly to twin MONOS memory either embedded in CMOS circuits or in a stand-alone application, and its fabrication method.
2. Description of the Related Art
A MONOS memory is one of typical semiconductor memories wherein carrier charge is stored in a gate insulator to have information nonvolatilely stored. The MONOS memory is of a laminated structure comprising a conductive gate (M), a top oxide film (O), a silicon nitride film (N), a tunnel oxide film (O) and a semiconductor wherein the carrier (electron or hole) is captured at a trapping level in the silicon nitride film to store the carrier charge
A MONOS memory is disclosed as the nonvolatile memory capable of reducing the programming voltage by E. Suzuki, H. Hiraishi, K. Ishii and Y. Hayashi, xe2x80x9cA Low-Voltage Alterable EEPROM with Metal-Oxide-nitride-Oxide and semiconductor (MONOS) Structuresxe2x80x9d, in IEEE Transaction on Electron Devices, Vol. ED-30, February 1983, p. 122). This MONOS memory is of a laminated structure comprising a conductive gate (M), a top oxide film (O), a silicon nitride film (N), a tunnel oxide film (O) and semiconductor. This structure has enabled the MONOS memory to stop hopping via the carrier trapping level in the silicon nitride film due to a potential barrier formed between the nitride film and the top oxide film, which resulted in making the nitride film as thin as possible. Further, carrier traps newly generated at the interface between the top oxide film and nitride film has enlarged a memory window to the extent it is possible to identify the stored information even if the entire insulator thickness is made thinner.
Twin MONOS individual cell structure was introduced in U.S. Pat. No. 6,255,166 to Seiki Ogura issued on Jul. 3, 2001. Its fabrication method was presented in U.S. patent application Ser. No. 09/994,084 to Ogura et al filed on Nov. 21, 2001. This invention also refers to an array structure of 4 bit-1 contact described in U.S. Pat. No. 6,469,935 to Hayashi et al issued Oct. 22, 2002, where four memory storage cells share one contact. These patents are herein incorporated by reference.
The invention proposes to simplify fabrication of the twin MONOS memory array. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention by adding only three additional mask levels. Conventional floating gate devices need ten or more extra masks. In the present invention, the unique twin MONOS process steps can be inserted into the standard CMOS process flow without any parameter modifications. The present invention also achieves increased endurance by means of reducing the widths of the sidewall control gate and underlying nitride storage region.
The twin MONOS fabrication method described prior to the present invention, such as in Ser. No. 09/994,084 requires a capping nitride layer with a thickness of between about 100 and 200 nm over the memory word gate, as shown in FIG. 2. It works as an etch stopper during chemical mechanical polishing (CMP) and enables the self-aligned word line wiring and/or self-aligned contact. Recently, salicidation over the CMOS gate polysilicon has become standard practice to reduce resistance. The capping nitride layer blocks salicidation so that the nitride over the CMOS gate polysilicon must be removed before the salicidation process. In this case, a mask is necessary to prevent removal of the capping nitride layer in the memory area. In the memory area, the capping nitride layer causes other problems. The structure of the 4 bit-1 contact memory array, such as described in U.S. Pat. No. 6,469,935 , does not need to expose the word line after CMP, so this structure does not have the capping nitride layer as a CMP etch stopper. The present invention proposes the elimination of the capping nitride layer over the gate polysilicon so that the nitride stripping mask is no longer necessary.
Any applied voltage during the twin MONOS device operation does not exceed 5V on the control gate during program operation. Therefore, the thick gate oxide as used in floating gate memory is not necessary. The gate oxides in the memory area can be the same as the CMOS oxides. Thus, no extra mask for the gate oxide in the memory area is needed.
The channel implantation under the control gate and memory LDD are maskless. Since the CMOS gate is patterned after the memory gate, the CMOS region is covered with the gate polysilicon and is not exposed to the memory implantations. The memory source/drain implantation is shared with the CMOS NMOS devices. No extra mask process is necessary for memory implantations.
The ultra short channel under the memory control gate is controlled by reducing the thickness of the control gate polysilicon to about 45 nm instead of using the disposable sidewall process as taught in Ser. No. 09/994,084. This not only simplifies the process, but also significantly improves the erase efficiency with hot hole injection. The spacer to define the offset to source/drain is shared with the CMOS process.
The present invention optimizes the extra mask steps added to the CMOS process to only 3:
1) Deep N-well mask to enable negative voltage application on NMOS,
2) Memory gate mask to define memory word gates, and
3) Memory control gate mask to form control gate contacts.
The present invention provides a simplified fabrication method to lower manufacturing costs.